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ISL6218
Data Sheet August 6, 2007 FN9101.6
Precision Single-Phase Buck PWM Controller for Intel Mobile Voltage Positioning IMVP-IVTM and IMVP-IV+TM
The ISL6218 Single-Phase Buck PWM control IC, with integrated half bridge gate driver, provides a precision voltage regulation system for advanced Pentium-M microprocessors in notebook computers. This control IC also features both input voltage feed-forward and average current mode control for excellent dynamic response, "Loss-less" current sensing using MOSFET rDS(ON), and user selectable switching frequencies from 250kHz to 500kHz per phase. The ISL6218 includes a 6-bit digital-to-analog converter (DAC) that dynamically adjusts the CORE PWM output voltage from 0.700V to 1.708V in 16mV steps, and conforms to the Intel IMVP-IVTM mobile VID specification. The ISL6218 also has logic inputs to select Active, Deep Sleep and Deeper Sleep modes of operation. A precision reference, remote sensing and proprietary architecture with integrated processor-mode compensated "Droop" provides excellent static and dynamic CORE voltage regulation. Another feature of the ISL6218 IC controller is the internal PGOOD delay circuit that holds the PGOOD pin low for 3ms to 12ms after the VCCP and VCC_MCH regulators are within regulation. This PGOOD signal is masked during VID changes. Output overvoltage and undervoltage are monitored and result in the converter latching off and PGOOD signal being held low. The overvoltage and undervoltage thresholds are 112% and 84% of the VID, Deep or Deeper Sleep setpoint. Overcurrent protection features a 32 cycle overcurrent shutdown. PGOOD, Overvoltage, Undervoltage and Overcurrent provide monitoring and protection for the microprocessor and power system. The ISL6218 IC is available in a 38 Ld TSSOP and 40 Ld QFN package.
Features
* IMVP-IVTM Compliant CORE Regulator * Single-Phase Power Conversion * "Loss-less" Current Sensing for Improved Efficiency and Reduced Board Area - Optional Discrete Precision Current Sense Resistor * Internal Gate Drive and Boot-Strap Diode * Precision CORE Voltage Regulation - 0.8% System Accuracy Over-temperature * 6-Bit Microprocessor Voltage Identification Input * Programmable "Droop" and CORE Voltage Slew Rate to Comply with IMVP-IVTM Specification * Discontinuous Mode Of Operation for Increased Light Load Efficiency in Deep and Deeper Sleep Mode * Direct Interface with System Logic (STP_CPU and DPRSLPVR) for Deep and Deeper Sleep Modes of Operation * Easily Programmable Voltage Setpoints for Initial "Boot", Deep Sleep and Deeper Sleep Modes * Excellent Dynamic Response - Combined Voltage Feed-Forward and Average Current Mode Control * Overvoltage, Undervoltage and Overcurrent Protection * Power-good Output with Internal Blanking During VID and Mode Changes * User Programmable Switching Frequency of 250kHz to 500kHz * Pb-Free Plus Anneal Available (RoHS Compliant)
Ordering Information
PART NUMBER ISL6218CV* ISL6218CVZ* (Note) ISL6218CVZA* (Note) ISL6218CRZ* (Note) PART MARKING ISL 6218CV ISL 6218CVZ ISL 6218CVZ ISL62 18CRZ TEMP. RANGE (C) -10 to +85 -10 to +85 -10 to +85 -10 to +85 PACKAGE 38 Ld TSSOP 38 Ld TSSOP (Pb-free) 38 Ld TSSOP (Pb-free) 40 Ld 6x6 QFN (Pb-free) PKG. DWG # M38.173 M38.173 M38.173 L40.6x6
*Add "-T" suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL6218 Pinouts
ISL6218 (38 LD TSSOP) TOP VIEW
VDD DACOUT DSV FSET NC EN DRSEN DSEN VID0 VID1 VID2 VID3 VID4 VID5 PGOOD EA+ COMP FB SOFT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 ISL6218 38 VBAT 37 ISEN 36 PHASE 35 UG 34 BOOT 33 VSSP 32 LG1 31 VDDP 30 NC 29 NC 28 NC 27 NC 26 NC 25 NC 24 VSEN 23 DRSV 22 STV 21 OCSET 20 VSS
ISL6218 (40 LD QFN) TOP VIEW
DACOUT PHASE BOOT 31 30 VSSP 29 LG 28 VDDP 27 NC 26 NC 25 NC 24 NC 23 NC 22 NC 21 NC 11 EA+ 12 COMP 13 FB 14 NC 15 SOFT 16 VSS 17 OCSET 18 STV 19 DRSV 20 VSEN VBAT FSET ISEN VDD DSV
40 EN DRSEN DSEN VID0 VID1 VID2 VID3 VID4 VID5 PGOOD 1 2 3 4 5 6 7 8 9 10
39
38
37
36
35
34
33
32
UG
NC
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ISL6218
Absolute Maximum Ratings
Supply Voltage VDD, VDDP . . . . . . . . . . . . . . . . . . . . . . -0.3 to +7V Battery Voltage, VBAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+25V Boot1 and UGATE1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+33V Phase1 and ISEN1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+28V Boot1 with respect to Phase1 . . . . . . . . . . . . . . . . . . . . . . . . . +6.5V UGATE1. . . . . . . . . . . . . . . . . . . . (Phase1 - 0.3V) to (Boot1 + 0.3V) All other pins . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VDD + 0.3V)
Thermal Information
Thermal Resistance (Typical) JA (C/W) JC (C/W) TSSOP Package (Note 1) . . . . . . . . . . . . 72 N/A QFN Package (Notes 2, 3) . . . . . . . . . . . 32 4.5 Maximum Operating Junction Temperature. . . . . . . . . . . . . . +125C Maximum Storage Temperature Range . . . . . . . . . .-65C to +150C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Supply Voltage, VDD, VDDP . . . . . . . . . . . . . . . . . . . . . . . +5V 5% Battery Voltage, VBAT . . . . . . . . . . . . . . . . . . . . . . . . . +5.6V to 21V Ambient Temperature. . . . . . . . . . . . . . . . . . . . . . . . .-10C to +85C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .-10C to +125C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTE: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 3. For JC, the "case temp" location is the center of the exposed metal pad on the package underside. 4. Limits established by characterization and are not production tested.
Electrical Specifications
PARAMETER INPUT SUPPLY POWER Input Supply Current, I(VDD)
Operating Conditions: VDD = 5V, TA = -10C to +85C, Unless Otherwise Specified. TEST CONDITIONS MIN TYP MAX UNITS
EN = 3.3V, DSEN = 0, DRSEN = 0 EN = 0V
4.39 4.10
1.4 1 4.45 4.20
4.5 4.37
mA A V V
POR (Power-On Reset) Threshold
VDD Rising VDD Falling
REFERENCE AND DAC System Accuracy DAC (VID0 to VID5) Input Low Voltage DAC (VID0 to VID5) Input High Voltage Maximum Output Voltage Minimum Output Voltage CHANNEL GENERATOR Frequency, fSW Adjustment Range ERROR AMPLIFIER DC Gain Gain-Bandwidth Product Slew Rate CL = 20pF CL = 20pF 100 18 4.0 dB MHz V/s RFset = 243k, 1% 225 250 250 275 500 kHz kHz Percent system deviation from programmed VID Codes @ 1.356 DAC Programming Input Low Threshold Voltage DAC Programming Input High Threshold Voltage -0.8 0.7 1.708 0.70 0.8 0.3 % V V V V
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Electrical Specifications
PARAMETER ISEN Full Scale Input Current Overcurrent Threshold Soft-Start Current Droop Current GATE DRIVER UGATE Source Resistance UGATE Source Current (Note 4) UGATE Sink Resistance UGATE Sink Current (Note 4) LGATE Source Resistance LGATE Source Current (Note 4) LGATE Sink Resistance LGATE Sink Current (Note 4) BOOTSTRAP DIODE Forward Voltage POWER GOOD MONITOR PGOOD Sense Current PGOOD Pull-Down MOSFET rDS(ON) Undervoltage Threshold (VSEN/VREF) Undervoltage Threshold (VSEN/VREF) PGOOD Low Output Voltage LOGIC THRESHOLD EN, DSEN, DRSEN Low EN, DSEN, DRSEN High PROTECTION Overvoltage Threshold (VSEN/VREF) DELAY TIME Delay Time from LGATE Falling to UGATE Rising Delay Time from UGATE Falling to LGATE Rising VDDP = 5V, BOOT to PHASE = 5V, UGATE - PHASE = 1V, LGATE = 1V VDDP = 5V, BOOT to PHASE = 5V, UGATE - PHASE = 1V, LGATE = 1V 10 10 18 18 30 30 ns ns VSEN Rising 112.0 % 2 1 V V VSEN Rising VSEN Falling
IPGOOD = 4mA
Operating Conditions: VDD = 5V, TA = -10C to +85C, Unless Otherwise Specified. (Continued) TEST CONDITIONS MIN TYP MAX UNITS
ROCSET = 110k (see Figure 10) SOFT = 0V ISEN = 32A 12.0
32 54 31 14
16.0
A A A A
500mA Source Current
VUGATE-PHASE = 2.5V
-
1 2 1 2 1 2 0.5 4
1.5 1.5 1.5 0.8 -
A A A A
500mA Sink Current
VUGATE-PHASE = 2.5V
500mA Source Current
VLGATE = 2.5V
500mA Sink Current
VLGATE = 2.5V
VDDP = 5V, Forward Bias Current = 10mA
0.57
0.68
0.74
V
2.43 56 -
63 85.0 84.0 0.26
82 0.4
mA % % V
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ISL6218 Functional Pin Description 38 Ld TSSOP
VDD DACOUT DSV FSET NC EN DRSEN DSEN VID0 VID1 VID2 VID3 VID4 VID5 PGOOD EA+ COMP FB SOFT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 ISL6218 38 VBAT 37 ISEN 36 PHASE 35 UG 34 BOOT 33 VSSP 32 LG 31 VDDP 30 NC 29 NC 28 NC 27 NC 26 NC 25 NC 24 VSEN 23 DRSV 22 STV 21 OCSET 20 VSS
VSEN
This pin is used for remote sensing of the microprocessor CORE voltage.
COMP
This pin provides connection to the error amplifier output.
FB
This pin is connected to the inverting input of the error amplifier.
EA+
This pin is connected to the non-inverting input of the error amplifier and is used for setting the "Droop" voltage.
STV
The voltage on this pin sets the initial start-up or "Boot" voltage.
SOFT
This pin programs the slew rate of VID changes, Deep Sleep and Deeper Sleep transitions, and soft-start after initializing. This pin is connected to ground via a capacitor, and to EA+ through an external "Droop" resistor.
VDD
This pin is used to connect +5V to the IC to supply all power necessary to operate the chip. The IC starts to operate when the voltage on this pin exceeds the rising POR threshold and shuts down when the voltage on this pin drops below the falling POR threshold.
DSEN
This pin connects to system logic "STP_CPU" and enables Deep Sleep mode of operation. Deep Sleep is enabled when a logic LOW signal is detected on this pin.
DRSEN
This pin connects to system logic "DPRSLPVR" and enables Deeper Sleep mode of operation when a logic HIGH is detected on this pin.
VDDP
This pin provides a low ESR bypass connection to the internal gate drivers for the +5V source.
PGOOD
This pin is used as an input and an output and is tied to the Vccp and Vcc_mch PGOOD signals. During start-up, this pin is recognized as an input, and prevents further slewing of the output voltage from the "Boot" level until PGOOD from Vccp and Vcc_mch is enabled High. After start-up, this pin has an open drain output used to indicate the status of the CORE output voltage. This pin is pulled low when the system output is outside of the regulation limits. PGOOD includes a timer for power-on delay.
VBAT
Voltage on this pin provides feed-forward battery information that adjusts the oscillator ramp amplitude.
FSET
A resistor from this pin to ground programs the switching frequency.
ISEN
This pin is used as current sense input from the converter channel phase node.
EN
This pin is connected to the system signal VR_ON and provides the enable/disable function for the PWM controller.
DACOUT
This pin provides access to the output of the Digital-toAnalog Converter.
OCSET
A resistor from this pin to ground sets the overcurrent protection threshold. The current from this pin should be between 10A and 25A (70k to 175k equivalent pull-down resistance).
DSV
The voltage on this pin provides the setpoint for output voltage during Deep Sleep Mode of operation.
DRSV
The voltage on this pin provides the setpoint for output voltage during Deeper Sleep Mode of operation.
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VID0, VID1, VID2, VID3, VID4, VID5
These pins are used as inputs to the 6-bit Digital-to-Analog converter (DAC). VID0 is the least significant bit and VID5 is the most significant bit.
VSSP
This pin is the return for the lower gate drive and is connected to power ground.
VSS
This pin provides connection for signal ground.
UG
This pin is the gate drive output to the high side MOSFETs.
Typical Application
Figure 1 shows a Single-Phase Synchronous Buck Converter circuit used to provide "CORE" voltage regulation for the Intel Pentium-M mobile processor using IMVP-IVTM voltage positioning. The circuit shows pin connections for the ISL6218 PWM controller in the 38 Ld TSSOP package.
LG
This pin is the gate drive output to the low side MOSFETs.
BOOT
This pin is connected to the Bootstrap capacitor for upper gate drive.
PHASE
This pin is connected to the phase node of the power channel.
VBATTERY +5VDC +5VDC
+VCC_CORE
VR_ON DPRSLPVR STP_CPU
VID
PWRGD
VBAT VDD ISEN DACOUT PHASE DSV UG FSET BOOT NC VSSP EN LG DRSEN VDDP DSEN VID0 NC ISL6218 VID1 NC TSSOP VID2 NC VID3 NC VID4 NC VID5 NC PGOOD VSEN DRSV EA+ STV COMP OCSET FB SOFT VSS
FIGURE 1. TYPICAL APPLICATION CIRCUIT FOR ISL6218 SINGLE-PHASE PWM CONTROLLER
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ISL6218 Block Diagram
VSEN PGOOD EN 1.3V + POWER-ON RESET (POR) VDD
+ OVP CONTROL AND FAULT LOGIC CLOCK AND SAWTOOTH GENERATOR THREE-STATE 112% RISING 102% FALLING 88% RISING 84% FALLING + UV + PWM PWM VBAT 1.75V FSET
32 COUNT CLOCK CYCLE DACOUT VSOFT SOFT EA+ VID0 SOFTSTART PHASE LOGIC
VDDP BOOT UG PHASE
VDDP LG VSSP
VID1 VID2 VID3 VID4 VID5 COMP FB IDROOP ISEN 1.75V IOCSET ISEN SAMPLE AND HOLD CHANNEL CURRENT SENSE VID D/A + E/A -
0.435
ISEN
OCSET STV DSV
0.5
+OC 2A
MUX DRSV VCORE REF
32 COUNT CLOCK CYCLE
DSEN DRSEN
VSS
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VID <3ms
CAPTURE VID CODE
VR_ON/EN VBOOT -12% >10s VCC-CORE t2 VVID
t1
PGOOD VCCP/VCC-MCH
3ms TO 12ms
PGOOD VCC-CORE
FIGURE 2. TIMING DIAGRAM SHOWING VR_ON, VCC_CORE AND PGOOD FOR VCC_CORE, VCCP AND VCC_MCH
Theory of Operation
Initialization
Once the +5VDC supply voltage (as connected to the ISL6218 VDD pin) reaches the Power-On Reset (POR) rising threshold, the PWM drive signals are held in "Three-State" or high impedance mode. This results in both the high side and low side MOSFETs being held off. Once the supply voltage exceeds the POR rising threshold, the controller will respond to a logic level high on the EN pin and initiate the soft-start interval. If the supply voltage drops below the POR falling threshold, POR shutdown is triggered and the PWM outputs are again driven to "Three-State". The system signal, VR_ON is directly connected to the EN pin of the ISL6218. Once the voltage on the EN pin rises above 2.0V, the chip is enabled and soft-start begins. The EN pin of the ISL6218 is also used to reset the ISL6218 for cases when an undervoltage or overcurrent fault condition has latched the IC off. Toggling the state of this pin to a level below 1.0V will re-enable the IC. For the case of an overvoltage fault, the VDD pin must be reset. During start-up, the ISL6218 regulates to the voltage on the STV pin. This is referred to as the "Boot" voltage and is labeled VBOOT in Figure 2. Once power good signals are received from the Vccp and Vcc_mch regulators, the ISL6218 will capture the VID code and regulate, within 3ms to 12ms, to this command voltage. The PGOOD pin of the ISL6218 is both an input and an output and is further described in "Fault Protection" on page 13.
Soft-Start Interval
Refer to Figure 2 and Figure 4. Once VDD rises above the POR rising threshold and the EN pin voltage is above the threshold of 2.0V, a soft-start interval is initiated. The voltage on the EA+ pin is the reference voltage for the regulator. The voltage on the EA+ pin is equal to the voltage on the SOFT pin minus the "Droop" resistor voltage, VDROOP. During start-up, when the voltage on SOFT is less than the "Boot" voltage VBOOT, a 130A current source I1, is used to slowly ramp up the voltage on the soft-start capacitor CSOFT. This slowly ramps up the reference voltage for the controller, and controls the slew rate of the output voltage. The STV pin is externally programmable and sets the start-up or "Boot" voltage VBOOT. The programming of this voltage level is explained in "STV, DSV and DRSV" on page 12. The ISL6218 PGOOD pin is both an input and an output. The system signal IMVP4_PWRGD is connected to power good signals from the Vccp and Vcc_mch supplies. The Intersil ISL6225 Dual Voltage Regulator is an ideal choice for the Vccp and Vcc_mch supplies. Refer to Figure 2 and Figure 4. Once the output voltage is within the "Boot" level regulation limits and a logic high PGOOD signal from the Vccp and Vccp_mch regulators is received, the ISL6218 is enabled to capture the VID code and regulate to that command voltage. The "Droop" current source IDROOP, is proportional to load current. This current source is used to reduce the reference voltage on EA+ by the voltage drop across the "Droop" resistor. A more in-depth explanation of "Droop" and the sizing of this resistor can be found in "Droop Compensation" on page 14.
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ISL6218
The choice of value for soft-start capacitor is determined by the maximum slew rate required for the application. An example calculation is shown in Equation 1. Using the I1 current source on the SOFT pin as 130A, and the slew rate of (10mV/s), the SOFT capacitor is calculated in Equation 1:
I 1s 0.012F CSOFT = SOURCE = 130A SlewRate 10mV (EQ. 1)
ISL6218
ERROR AMPLIFIER IDROOP
Gate Drive Signals
The ISL6218 provides internal gate drive for a single channel, Synchronous Buck, Core Regulator. The ISL6218 was designed with a 4A, low side gate current sink ability, and a 2A, low-side gate current source ability to efficiently drive the latest, high performance MOSFETs. This feature will provide the system designer with flexibility in MOSFET selection as well as optimum efficiency during all modes of operation.
+
SOFT
EA+ RDROOP + VDROOP CSOFT
Frequency Setting
The power channel switching frequency is set up by a resistor from the FSET pin to ground. The choice of FSET resistance for a desired switching frequency can be approximated using Figure 3. The switching frequency is designed to operate between 250kHz and 500kHz per phase.
FIGURE 4. SOFT-START TRACKING CIRCUITRY SHOWING INTERNAL CURRENT SOURCES AND "DROOP" FOR ACTIVE, DEEP AND DEEPER SLEEP MODES OF OPERATION
CORE Voltage Programming
The voltage identification pins (VID0, VID1, VID2, VID3, VID4 and VID5) set the DAC output voltage. These pins do not have internal pull-up or pull-down capability. These pins will recognize 1.0V, 3.3V or 5.0V CMOS logic. Table 1 shows the command voltage, VDAC for the 6 bit VID codes. The IC responds to VID code changes as shown in Figure 5. PGOOD is masked between these transitions.
250
TABLE 1. INTEL IMPV-IV VID CODES VID5 VID4 VID3 VID2 VID1 VID0 VDAC
0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
1.708 1.692 1.676 1.660 1.644 1.628 1.612 1.596 1.580 1.564 1.548 1.532 1.516 1.500 1.484 1.468 1.452 1.436 1.420 1.404
FSET RESISTOR VALUE (k)
200
0 0
150
0 0
100
0 0
50
0 0
0
250k
500k
750k
1M
0 0 0 0 0
CHANNEL SWITCHING FREQUENCY, fSW (Hz)
FIGURE 3. CHANNEL SWITCHING FREQUENCY vs RFSET
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TABLE 1. INTEL IMPV-IV VID CODES (Continued) VID5 VID4 VID3 VID2 VID1 VID0 VDAC TABLE 1. INTEL IMPV-IV VID CODES (Continued) VID5 VID4 VID3 VID2 VID1 VID0 VDAC
0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1
1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
1.388 1.372 1.356 1.340 1.324 1.308 1.292 1.276 1.260 1.244 1.228 1.212 1.196 1.180 1.164 1.148 1.132 1.116 1.100 1.084 1.068 1.052 1.036 1.020 1.004 0.988 0.972 0.956 0.940 0.924 0.908 0.892 0.876 0.860 0.844 0.828 0.812 0.796 0.780 0.764
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
0 0 1 1
0 1 0 1
0.748 0.732 0.716 0.700
Active, Deep Sleep and Deeper Sleep Modes
The ISL6218 Single-Phase Controller is designed to control the CORE output voltage as per the IMVP-IVTM specifications for Active, Deep Sleep, and Deeper Sleep Modes of Operation. After initial start-up, a logic high signal on DSEN and a logic low signal on DRSEN signals the ISL6218 to operate in Active mode (refer to Table 2). This mode will recognize VID code changes and regulate the output voltage to these command voltages. A logic low signal present on STPCPU (pin DSEN), with a logic low signal on DPRSLPVR (pin DRSEN) signals the ISL6218 to reduce the CORE output voltage to the Deep Sleep level, the voltage on the DSV pin. A logic high on DPRSLPVR (pin DRSEN), with a logic low signal on STPCPU (pin DSEN), signals the ISL6218 controller to further reduce the CORE output voltage to the Deeper Sleep level, which is the voltage on the DRSV pin. Deep Sleep and Deeper Sleep voltage levels are programmable and are explained in "STV, DSV and DRSV" on page 12.
TABLE 2. OUTPUT VOLTAGE AS A FUNCTION OF DSEN AND DRSEN LOGIC STATES DSEN STP_CPU DRSEN DPRSLPVR MODE OF OPERATION OUTPUT VOLTAGE
1 0 0 1
0 0 1 1
Active Deep Sleep Deeper Sleep Deeper Sleep
VID DSV DRSV DRSV
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VID[0..5] CURRENT VID CODE <600ns CURRENT VOLTAGE LEVEL NEW VOLTAGE LEVEL NEW VID CODE
VCC_CORE
PGOOD
HIGH
FIGURE 5. PLOT SHOWING TIMING OF VID CODE CHANGES AND CORE VOLTAGE SLEWING AS WELL AS PGOOD MASKING
VID[0..5] VID CODE REMAINS THE SAME
STP_CPU (DSEN) VID COMMAND VOLTAGE VCC_CORE VDEEP SLEEP <3s
FIGURE 6. CORE VOLTAGE SLEWING TO 98.8% OF PROGRAMMED VID VOLTAGE FOR A LOGIC LEVEL LOW ON DSEN
VID[0..5]
VID CODE REMAINS THE SAME
STP_CPU (DSEN) DEEPER SLEEP DPRSLPVR (DRSEN) VCC_CORE VDEEP VDEEPER SHORT DPRSLP CAUSES VCC_CORE TO RAMP-UP
FIGURE 7. VCORE RESPONSE FOR DEEPER SLEEP COMMAND
Deep Sleep Enable (DSEN) and Deeper Sleep Enable (DRSEN)
Table 2 shows logic states controlling modes of operation Figure 6 and Figure 5 show the timing for transitions entering and exiting Deep Sleep Mode and Deeper Sleep Mode, controlled by the system signals STPCPU and DPRSLPVR. Pins DSEN (Deep Sleep Enable) and DRSEN (Deeper Sleep Enable) of the ISL6218 are connected to these 2 signals, respectively. For the case when DSEN is logic high, and DRSEN is logic low, the controller will operate in Active Mode and regulate the output voltage to the VID commanded DAC voltage minus the voltage "Droop" as determined by the load current. Voltage "Droop" is the reduction of output voltage proportional to output current.
When a logic low is seen on the DSEN and DRSEN is logic low the controller will then regulate the output voltage to the voltage seen on the DSV pin minus "Droop". When DSEN is logic low and DRSEN is logic high the controller will operate in Deeper Sleep mode. The ISL6218 will then regulate to the voltage seen on the DRSV pin minus "Droop". Deep and Deeper Sleep voltage levels are programmable and explained in "STV, DSV and DRSV" on page 12. DISCONTINUOUS OPERATION - PSI The ISL6218 Single-Phase PWM controller is a Synchronous Buck Regulator. However, in Deep and Deeper Sleep modes where the load current is low, the controller operates as a standard buck regulator. This mode of operation acts to eliminate negative inductor current by truncating the low side MOSFET gate drive pulse, and
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ISL6218
shutting off the low side MOSFET. This "Three-State" mode will hold both upper and low side MOSFETs off during the time that the Low Side MOSFET would normally be on. This "Diode Emulation" is initiated when the current, as sensed through the low side MOSFET, is negative. This event triggers the "Three-State" mode until the next PWM cycle. This Discontinuous operation improves efficiency by preventing the reverse conduction of current through the low side MOSFET. This eliminates conduction loss and output discharge. Discontinuous operation is enabled in Deep and Deeper Sleep modes and is based solely on current feedback. Due to this ISL6218's ability to sense zero current and prevent discharging through the low side MOSFETs during light loads, the ISL6218 meets the requirements for PSI without requiring any external signals.
BATTERY V REF = 1.75V I OCSET OCSET VBAT R1 36.5k 1.200V STV DACOUT R2 30.1k 0.750V DRSV SOFT R3 49.9k DSV GND 0.012F 1.21k VID COMMAND VOLTAGE ISL6218
98.8% DACOUT 98.8k
STV, DSV and DRSV
START-UP "BOOT" VOLTAGE - STV The Start-up, or "Boot," voltage is programmed by an external resistor divider network from the OCSET pin (refer to Figure 8). Internally, a 1.75V reference voltage is output on the OCSET pin. The start-up voltage is set through a voltage divider from the 1.75V reference at the OCSET pin. The voltage on the STV pin will be the controller regulating voltage during the start-up sequence. Once the PGOOD pin of the ISL6218 controller is externally enabled high by the Vccp and Vcc_mch controllers, the ISL6218 will then ramp, after a 10s delay, to the voltage commanded by the VID setting minus "Droop". DEEP SLEEP VOLTAGE- DSV The Deep Sleep voltage is programmed by an external voltage divider network from the DACOUT pin (Refer to Figure 8). The DACOUT pin is the output of the VID digitalto-analog converter. By having the Deep Sleep voltage setup from a resistor divider from DAC, the Deep Sleep voltage will be a constant percentage of the VID. Through the voltage divider network, Deep Sleep voltage is set to 98.8% of the programmed VID voltage, as per the IMVP-IVTM specification. The IC enters the Deep Sleep mode when the DSEN is low and the DRSEN pin is low as shown in Figure 6 and Figure 5. Once in Deep Sleep Mode, the controller will regulate to the voltage seen on the DSV pin minus "Droop". DEEPER SLEEP VOLTAGE - DRSV The Deeper Sleep voltage, DRSV, is programmed by an external voltage divider network from the 1.75V reference on the OCSET pin (Refer to Figure 8). In Deeper Sleep mode the ISL6218 controller will regulate the output voltage to the voltage present on the DRSV pin minus "Droop". The IC enters Deeper Sleep mode when DRSEN is high and DSEN is low, as shown in Figure 5.
FIGURE 8. CONFIGURATIONS FOR BATTERY INPUT, OVERCURRENT SETTING AND START, DEEP SLEEP AND DEEPER SLEEP VOLTAGE
OVERCURRENT SETTING - OCSET The ISL6218 overcurrent protection essentially compares a user-selectable overcurrent threshold to the scaled and sampled output current. An overcurrent condition is defined when the sampled current is equal to or greater than the threshold current. A step by step process to the user-desired overcurrent set point is detailed next. Step 1: Setting the Overcurrent Threshold The overcurrent threshold is represented by the DC current flowing out of the OCSET pin (See Figure 8). Since the OCSET pin is held at a constant 1.75V, the user need only populate a resistor from this pin to ground to set the desired overcurrent threshold, IOCSET. The user should pick a value of IOCSET between 10A and 15A. Once this is done, use Ohm's Law to determine the necessary resistor to place from OCSET to ground: ROCSET = 1.75 V = R1 + R 2 + R 3 IOCSET
(EQ. 2)
For example, if the desired overcurrent threshold is 15A, the total resistance from OCSET must equal 117k. Step 2: Selecting ISEN Resistance for Desired Overcurrent Level After choosing the IOCSET level, the user must then decide what level of total output current is desired for overcurrent. Typically, this number is between 150% and 200% of the maximum operating current of the application. For example, if the max operating current is 27A, and the user chooses 150% overcurrent, the ISL6218 will shut down if the output current exceeds 27A*1.5 or 40A. According to the "Block Diagram" on page 7, Equation 3 should be used to determine RISEN once the overcurrent level, IOC, is chosen.
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ISL6218
r(DSON) M
RISEN =
IOC
0.2175
IOCSET - 2A
- 130
(EQ. 3)
RST IPGT START t 3ms TO 12ms
S SET Q R Q CLR t ~100ns
ISL6218 START PGOOD
3.3V 1.2k
3.3V 10k 3.3V 10k
ISL6225 PGOOD VCCP
In Equation 3, M represents the number of Low-Side MOSFETs. Using the examples above (IOC = 40A, IOCSET = 15A) and substituting the values M = 2, rDS(ON) = 4.5m, RISEN is calculated to be 1370. Step 3: Thermal Compensation for rDS(ON) (if desired) If PTCs are used for thermal compensation, then RISEN is found using the room temperature value of rDS(ON). If standard resistors are used for RISEN, then the "HOT" value of rDS(ON) should be used for this calculation. MOSFET rDS(ON) sensing provides advantages in cost, efficiency, and board area. However, if more precise current feedback is desired, a discrete Precision Current Sense Resistor RPOWER may be inserted between the SOURCE of each channel's lower MOSFET and ground. The small RISEN resistor, as previously described, is then replaced with a standard 1% resistor and connected from the ISEN pin of the ISL6218 controller to the SOURCE of the lower MOSFET. BATTERY FEED-FORWARD COMPENSATION - VBAT As shown in Figure 8, the ISL6218 incorporates Battery Voltage Feed-Forward Compensation. This compensation provides a constant Pulse Width Modulator Gain independent of battery voltage. An understanding of this gain is required for proper loop compensation. The Battery Voltage is connected directly to the ISL6218 by the VBAT pin, and the gain of the system ramp modulator is a constant 6.0. FAULT PROTECTION The ISL6218 protects the CPU from damaging stress levels. The overcurrent trip point is integral in preventing output shorts of varying degrees from causing current spikes that would damage a CPU. The output overvoltage and undervoltage detection features insure a safe window of operation for the CPU. OUTPUT VOLTAGE MONITORING VSEN is connected to the local CORE Output Voltage and is used for PGOOD, undervoltage and overvoltage sensing only. (Refer to the "Block Diagram" on page 7). The VSEN voltage is compared with two voltage levels that indicate an overvoltage or undervoltage condition of the output. Violating either of these conditions results in the PGOOD pin toggling low to indicate a problem with the output voltage.
PGOOD
VCCP_MC
CPU-UP = UV AND OV
CLK_ENABLE IMVP4_PWRGD
FIGURE 9. INTERNAL PGOOD CIRCUITRY FOR THE ISL6218 CORE VOLTAGE REGULATOR
PGOOD As previously described, the ISL6218 PGOOD pin operates as both an input and an output. During start-up, the PGOOD pin operates as an input. Refer to Figure 9. As per the IMVP-IVTM specification, once the ISL6218 CORE regulator regulates to the "Boot" voltage, it waits for the PGOOD logic HIGH signals from the Vccp and Vcc_mch regulators. The Intersil ISL6225 is a perfect choice for these two supplies as it is a dual regulator and has independent PGOOD functions for each supply. Once these two supplies are within regulation, PGOODVccp and PGOODVcc_mch will be high impedance, and will allow the PGOOD of the ISL6218 to sink approximately 2.6mA to ground through the internal MOSFET, shown in Figure 9. The ISL6218 detects this current and starts an internal PGOOD timer. The current sourced into the PGOOD pin is critical for proper start-up operation. The pullup resistor, Rpull-up is sized to give a minimum of 2.6mA of current sourced into the PGOOD pin from 3.3V supply. As given in the "Electrical Specifications" table on page 4, the PGOOD MOSFET rDS(ON) is given as 82 maximum. If a 3.3V source is used as the Pull-up, then the Pull-up resistor is given Equation 4:
RPullup = VSOURCE 3.3 - 0.05 (3.3 ) - rDSON (max ) = - 82 = 1.2k 2.6mA 2.6mA (EQ. 4)
where VSOURCE is the supply minus 5% for tolerance. This will insure that the required PGOOD current will be sourced into the PGOOD pin for worst case conditions of low supply and largest MOSFET rDS(ON). Once the proper level of PGOOD current is detected, the ISL6218 then captures the VID and regulates to this value. The PGOOD timer is a function of the internal clock and switching frequency. The internal PGOOD delay can be calculated in Equation 5: PGOOD Timer Delay = 3072 / fSW
(EQ. 5)
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ISL6218
The ISL6218 controller regulates the CORE output voltage to the VID command and once the timer has expired, the PGOOD output is allowed to go high. Note, the PGOOD functions of the VCC_CORE, Vccp and Vcc_mch regulators are wire OR'd together to create the system signal "IMVP4_PWRGD". If any of the supplies fall outside the regulation window, their respective PGOOD pins are pulled low, which forces IMVP4_PWRGD low. PGOOD of the ISL6218 is internally disabled during all VID and Mode transitions. OVERVOLTAGE The VSEN voltage is compared with an internal overvoltage protection (OVP) reference set to 112% of the VID voltage. If the VSEN voltage exceeds the OVP reference, a comparator simultaneously sets the OV latch and triggers the PWM output low. The drivers turn on the lower MOSFETs, shunting the converter output to ground. Once the output voltage falls below 102% of the set point, the high side and low side PWM outputs are held in "Three-State". This prevents dumping of the output capacitors back through the output inductors and lower MOSFETs, which would cause a negative voltage on the CORE output. This architecture eliminates the need of a high current, Schottky diode on the output. If the overvoltage conditions persist, the PWM outputs are cycled between output low and output "off", similar to a hysteretic regulator. The OV latch is reset by cycling the VDD supply voltage to initiate a POR. Depending on the mode of operation, the overvoltage setpoint is 112% of the VID, Deep or Deeper Sleep setpoint. UNDERVOLTAGE The VSEN pin is also compared to an Undervoltage (UV) reference, which is set to 84% of the VID, Deep or Deeper Sleep setpoint, depending on the mode of operation. If the VSEN voltage is below the UV reference for more than 32 consecutive phase clock cycles, the power good monitor triggers the PGOOD pin to go low and latches the chip off until power is reset to the chip or the EN pin is toggled. OVERCURRENT The RISEN resistor scales the voltage sampled across the lower MOSFET and provides current feedback ISEN, which is proportional to the output current (refer to Figure 10). After current sensing function, ISEN is obtained (refer to the "Block Diagram" on page 7 and Figure 10). ISEN is compared with an internally generated overcurrent trip threshold that is propotional to the current sourced from the OCSET pin, IOCSET. The overcurrent trip current source is programmable and described in "Overcurrent Setting - OCSET" on page 12. If ISEN exceeds the IOCSET level, an up/down counter is enabled. If ISEN' does not fall below IOCSET within 32 phase cycle counts, the PGOOD pin transitions low and latches the chip off. If normal operation resumes within the 32 phase cycle count window, the controller will continue to operate normally. NOTE: Due to "DROOP", there is inherent Current limit since load current cannot exceed the amount that would command an output voltage lower than 84% of the VID voltage. This would result in an undervoltage shutdown and would also cause the PGOOD pin to transition low and latch the chip off. CONTROL LOOPS Figure 10 shows a simplified diagram of the voltage regulation and current control loops for a Single-Phase converter. Both voltage and current feedback are used to precisely regulate voltage and tightly control output current IL1. The voltage loop is comprised of the Error Amplifier, Comparators, Internal Gate Drivers and MOSFETs. The Error Amplifier drives the modulator to force the FB pin to the IMVP-IVTM reference minus "Droop". VOLTAGE LOOP The output CORE voltage feedback is applied to the Error Amplifier through the compensation network. The signal seen on the FB pin will drive the Error Amplifier output either high or low, depending upon the CORE voltage. A CORE voltage level that is lower than the IMVP-IVTM reference, as output from the 6-bit DAC, causes the amplifier output to move towards a higher output voltage level. The amplifier output voltage is applied to the positive input of the comparator. Increasing Error Amplifier voltage results in increased Comparator output duty cycle. This increased duty cycle signal is passed through the PWM circuit to the internal gate drive circuitry. The output of the internal gate drive is directly connected to the gate of the MOSFETs. Increased duty cycle, or ON-time, for the high side MOSFET transistors, results in increased output voltage (VCORE) to compensate for the low output voltage sensed. DROOP COMPENSATION Microprocessors and other peripherals tend to change their load current demands from near no-load to full load, often during operation. These same devices require minimal output voltage deviation during a load step. A high di/dt load step will cause an output voltage spike. The amplitude of the spike is dictated by the output capacitor ESR multiplied by the load step magnitude plus the output capacitor ESL times the load step di/dt. A positive load step produces a negative output voltage spike and vice versa. A large number of low-series-impedance capacitors are often used to prevent the output voltage deviation from exceeding the tolerance of some devices. One widely accepted solution to this problem is output voltage "Droop", or active voltage positioning. As shown in the block diagram, the sensed current (ISEN) is used to control the "Droop" current source, IDROOP. The "Droop" current source is a controlled current source and is proportional to output current. This current source is
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ISL6218
R1 COMP
C2 FB R2 C1
CDCPL VSEN RISEN VrDS(ON)+ PHASE VIN L01
ERROR AMPLIFIER EA+ _ VDROOP + RDROOP SOFT + IDROOP IMVP IV REFERENCE IOCSET VERROR1 +
OVER-UNDER VOLTAGE UG1 PWM CIRCUIT Q2 LG1
Q1
VCORE RLOAD
COMPARATOR
IL1 VrDS(ON) +
COUT
CSOFT
OVER CURRENT ISEN'
ISEN ISL6218
CURRENT SENSING
ISEN1 ISEN1
FIGURE 10. SIMPLIFIED BLOCK DIAGRAM OF THE ISL6218 VOLTAGE AND CURRENT CONTROL LOOPS FOR THE SINGLE CHANNEL REGULATOR.
approximately 1/2 of the ISEN, as shown in the "Block Diagram" on page 7. The Droop current is sourced out of the SOFT pin through the Droop resistor and returns through the EA+ pin. This creates a "Droop" voltage VDROOP, that subtracts from the IMVP-IVTM reference voltage on SOFT to generate the voltage setpoint for the CORE regulator. Full load current for the Intel IMVP-IVTM Thin and Light specification is 25A. Knowing that the Droop Current, sourced out of the SOFT pin will be 1/2 of the ISEN, a "Droop" resistor, RDROOP, can be selected to provide the amount of voltage "Droop" required at full load. The selection of this resistor is explained "Selection of RDROOP" on page 15. SELECTION OF RDROOP Figure 11 shows a static "Droop" load line for the 1.484V Active Mode. The ISL6218, as previously mentioned, allows the programming of the load line slope by the selection of the RDROOP resistor. As per the Intel IMVP-IVTM and IMVP-IV+TM specification, Droop = 0.003 (). Therefore, 25A of full load current equates to a 0.075V Droop output voltage from the VID setpoint. RDROOP can be selected based on RISEN which is calculated through Equation 3, r(DS(ON) and Droop, as per the "Block Diagram" on page 7 or Equation 6:
RDROOP = 2.3 (Droop ) RISEN () r(DSON) M
(EQ. 6)
VOUT, HI VOUT, NOM VOUT, LO
(0A, 1.506V) (0A, 1.484V) (0A, 1.462V)
(25A, 1.431V) (25A, 1.409V) (25A, 1.387V)
-3m LOAD LINE I OUT, NL IOUT, MID IOUT, MAX
STATIC TOLERANCE BANDS NOMINAL "DROOP" LOAD LINE
FIGURE 11. IMVP-IVTM ACTIVE MODE STATIC LOAD LINE
Component Selection Guidelines
Output Capacitor Selection
Output capacitors are required to filter the output inductor current ripple, and supply the transient load current. The filtering requirements are a function of the channel switching frequency and the output ripple current. The load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. The microprocessor used for IMVP-IVTM will produce transient load rates as high as 30A/ns. High frequency ceramic capacitors are used to supply the initial transient current, and slow the rate-of-change seen by the bulk capacitors. Bulk filter capacitor values are generally determined by the ESR (Effective Series Resistance) and voltage rating requirements, rather than actual capacitance requirements. To meet the stringent requirements of IMVP-IVTM, (15) 2.2F, 0612 "Flip Chip" high frequency, ceramic capacitors are placed very close
FN9101.6 August 6, 2007
15
ISL6218
to the Processor power pins; they are placed carefully so they do not to add inductance in the circuit board traces, which could cancel the usefulness of these low inductance components. Specialized low-ESR capacitors intended for switching regulator applications are recommended for the bulk capacitors. The bulk capacitors ESR and ESL determine the output ripple voltage and the initial voltage drop following a high slew-rate transient edge. Recommended are at least (4) 4V, 220F Sanyo Sp-Cap capacitors in parallel, or (5) 330F SP-Cap style capacitors. These capacitors provide an equivalent ESR of less than 3m. These components should be laid out very close to the load. As the sense trace for VSEN may be long and routed close to switching nodes, a 1.0F ceramic decoupling capacitor is located between VSEN and ground at the ISL6218 package.
MOSFET Selection and Considerations
For the Intel IMVP-IVTM application that requires up to 20A of current, it is suggested that Single-Phase channel operation, with a minimum of (4) MOSFETs per channel, be implemented. This configuration would be: (2) High Switching Frequency, Low Gate Charge MOSFET for the Upper; and (2) Low rDS(ON) MOSFETs for the Lowers. In high-current PWM applications, the MOSFET power dissipation, package selection and heatsink are the dominant design factors. The power dissipation includes two loss components: conduction loss and switching loss. These losses are distributed between the upper and lower MOSFETs according to duty cycle of the converter. Refer to Equations 8 and 9. The conduction losses are the main component of power dissipation for the lower MOSFETs. Only the upper MOSFETs have significant switching losses, since the lower devices turn on and off into near zero voltage. The following equations assume linear voltagecurrent transitions and do not model power loss due to the reverse-recovery of the lower MOSFET's body diode. The gate-charge losses are dissipated in the ISL6218 drivers and do not heat the MOSFETs; however, large gate-charge increases the switching time tSW, which increases the upper MOSFET switching losses. Ensure that both MOSFETs are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications.
Output Inductor Selection
The output inductor is selected to meet the voltage ripple requirements and minimize the converter response time to a load transient. The inductor selected for the power channel determines the channel ripple current. Increasing the value of inductance reduces the total output ripple current and total output voltage ripple, but will slow the converter response time to a load transient. One of the parameters limiting the converter's response time to a load transient is the time required to slew the inductor current from its initial current level to the transient current level. During this interval, the difference between the two levels must be supplied by the output capacitance. Minimizing the response time can minimize the output capacitance required. The channel ripple current is approximated by Equation 7: V - VOUT VOUT ICH = IN * FSW * L VIN
PUPPER =
IO 2 xrDS (ON ) x VOUT VIN
I x VIN x t SW x FSW +O 2
(EQ. 8)
PLOWER =
(EQ. 7)
IO 2 x rDS (ON ) x (VIN - VOUT ) VIN
(EQ. 9)
Input Capacitor Selection
Use a mix of input bypass capacitors to control the voltage overshoot across the MOSFETs. Use ceramic capacitors for the high frequency decoupling and bulk capacitors to supply the RMS current. Small ceramic capacitors must be placed very close to the upper MOSFET to suppress the voltage induced in the parasitic circuit impedances. Two important parameters to consider when selecting the bulk input capacitor are the voltage rating and the RMS current rating. For reliable operation, select a bulk capacitor with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline.
Typical Application - Single Phase Converter Using ISL6218 PWM Controller
Figure 12 shows the ISL6218, Synchronous Buck Converter circuit, which is used to provide the CORE voltage regulation for the Intel IMVP-IVTM application. The circuit uses a single power channel to deliver up to 20A steady state current, and has a 330kHz channel switching frequency. For thermal compensation, a PTC resistor is used as sense resistors. The Output capacitance is less than 3m of ESR and is (4) 220F, 4V Sp-Cap parts in parallel with (35) high frequency, 10F ceramic capacitors.
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FN9101.6 August 6, 2007
ISL6218
VBATTERY +5VDC 8 x 10F 2 x IRF7811W 1F 98.8k__1% BAT54 0.027F 174k_1% 1.2k__1% VDD DACOUT DSV FSET NC EN DRSEN DSEN VID0 ISL6218 VID1 TSSOP VID2 VID3 VID4 VID5 PGOOD EA+ COMP FB SOFT VBAT ISEN PHASE UG BOOT VSSP LG VDDP NC NC NC NC NC NC VSEN DRSV STV OCSET VSS 2 x SI4362DY 0.33F 10_1% 0.8H 1.5k_1%PTC ETQ-P3H0R8BA 4 x 220F AND 35 x 10F +VCC_CORE
+5VDC
VR_ON DPSLP
1R5_5%
4.7F
VID
4.64k_1%
3300pF 0.012F 14k_1% 36.5k_1% 1800pF 30.1k_1% 49.9k_1%
No-POP
No-POP 3.57k_1%
560pF
ANALOG
POWER
FIGURE 12. TYPICAL APPLICATION CIRCUIT FOR THE ISL6218, IMVP-IVTM CORE VOLTAGE REGULATOR
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FN9101.6 August 6, 2007
ISL6218
Package Outline Drawing
L40.6x6
40 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 3, 10/06
4X 4.5 6.00 A B 6 PIN 1 INDEX AREA 30 31 36X 0.50 40 1 6 PIN #1 INDEX AREA
4 . 10 0 . 15 6.00
21 (4X) 0.15 20 TOP VIEW 40X 0 . 4 0 . 1 BOTTOM VIEW 11
10
0.10 M C A B 4 0 . 23 +0 . 07 / -0 . 05
SEE DETAIL "X" 0.10 C BASE PLANE SIDE VIEW ( 36X 0 . 5 ) SEATING PLANE 0.08 C C
0 . 90 0 . 1 ( 5 . 8 TYP ) ( 4 . 10 )
C ( 40X 0 . 23 ) ( 40X 0 . 6 ) TYPICAL RECOMMENDED LAND PATTERN
0 . 2 REF
5
0 . 00 MIN. 0 . 05 MAX. DETAIL "X"
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature.
18
FN9101.6 August 6, 2007
ISL6218 Thin Shrink Small Outline Plastic Packages (TSSOP)
N INDEX AREA E E1 -B1 2 3 0.05(0.002) -AD -CSEATING PLANE A 0.25 0.010 L 0.25(0.010) M GAUGE PLANE BM
M38.173
38 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-153-BD-1 ISSUE F) INCHES SYMBOL A A1 A2 b c D MIN 0.002 0.031 0.0075 0.0035 0.378 0.169 0.246 0.0177 38 0o 8o 0o MAX 0.047 0.006 0.051 0.0106 0.0079 0.386 0.177 0.256 0.0295 MILLIMETERS MIN 0.05 0.80 0.17 0.09 9.60 4.30 6.25 0.45 38 8o MAX 1.20 0.15 1.05 0.27 0.20 9.80 4.50 6.50 0.75 NOTES 9 3 4 6 7 Rev. 0 1/03
e
b 0.10(0.004) M C AM BS
A1 0.10(0.004)
A2 c
E1 e E L N
0.0197 BSC
0.500 BSC
NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-BD-1, Issue F. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 19
FN9101.6 August 6, 2007

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